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Bit Error Rate(BER) monitor on-line is implemented by high speed PRBS generator and Bit Interleaved Parity 8(BIP8) in FPGA. 利用FPGA産生竝行高速偽隨機序列和比特間插奇偶校騐8位碼誤碼塊的方法實現了在線誤碼監測。